Report from WCA: 'Radio Free Intel'
Following up on my previous interest in the Intel software defined radio publicity, I wandered over to the WCA meeting yesterday afternoon, to take in a presentation on the topic, given by Steve Pawlowski, Intel Fellow and Director in their Microprocessor Technology Laboratory, and also apparently technical head of the aforementioned initiative. A few observations:
This is still very much a 'big R' research project. The goal is the eventual integration of software defined baseband processor, RF transceivers, and antenna switches / tunable filters onto one chip, which might eventually become a portion of the die for Intel's platform processors. Every one of those elements poses a serious design and fabrication challenge.
Intel seems to be banking on MEMS technology for the switching and filtering frontend, but most of the talk and discussion actually centered on the baseband processor architecture. This work is being done in conjunction with the Berkeley Wireless Research Center, specifically in collaboration with Bob Broderson's group. Pawlowski mentioned that a number of UCB grad students had been pulled in house to work on the project, and were proving useful since they "don't know what's impossible." For more background information on work at the BWRC, check out this page of presentations.
The basic approach to software radio is a reconfigurable processor, similar in some ways to finer grain designs such as that by Quicksilver. In this case, the building blocks contain radio processing specific functions such as filter convolutions, as well as more general purpose functions. Some of the initial design thoughts are given in this year old presentation. Apparently the design was also presented at the 2003 VLSI Symposium in Kyoto, but I haven't found that on the net. These blocks are in a meshed, asynchronous, parallel configuration with dynamically programmable dataflows. In theory, the total throughput of the system should be on the order of that once achieved in the Cray XMP supercomputer. (In a handset. What fun!)
Of course, we're talking simulations, so far as I could tell. The goal for next year is to tape out the functional blocks. There's no design and programming methodology or toolset for the architecture as yet. Integrating baseband processor and other elements such as MEMS onto one chip is going to be fun; getting the whole affair onto a MPU die, with all of its RF noise, is going to require some novel feats in isolation, as was pointed out by the audience. Timeline? Maybe 2008 for first product - 2010 for full integration, adding a bit onto the dates given in the talk. I'd normally add even more for the cycle of selling the idea to mainline product management, but the high level at which positioning statements re 'Intel Radio' are being made seems to imply a mandate.
So, this isn't going to kill off high priced and less functional SDR-targeted ventures or components real soon now, but Intel seems willing to take on some extremely hairy engineering chores to explore SDR. One might almost think they see challanges of this sort being closer to the design edge, and offering better ROI in the long term, than banging away on next generation MPU designs. Hmmm....